From RTL development and functional verification to synthesis, physical implementation, timing closure, and signoff, Synopsys EDA technologies enable engineering teams to design increasingly complex semiconductor devices with greater confidence, productivity, and performance.
We help organizations successfully deploy, adopt, and utilize Synopsys solutions through technical consulting, training, installation support, and workflow optimization.
Design Families and Verification Families
Design Families
- Digital Design Family for RTL-to-GDSII work on SoCs, processors, and any synthesizable digital logic.
- Custom Design Family for analog, mixed-signal, RF, or memory blocks where SPICE accuracy and hand-driven layout matter.
- FPGA-based Design if you’re shipping FPGA-based hardware or using FPGAs to prototype an ASIC before tape-out.
Most teams use more than one, and all three share a unified data model so designs flow between them without rework.
1. Digital Design:
A fusion-driven, single-data-model platform that unifies the entire RTL-to-signoff flow with integrated 3DIC and silicon lifecycle management — delivering maximum PPA entitlement and significant productivity gains across digital design.
- 3DIC Compiler
- Physical Implementation
- RTL Design and Synthesis
- Test Automation
- Flow Automation
- Design Analytics
- Physical Verification
- Signoff
2. Custom Design:
A unified suite of design, layout, simulation, and verification tools — anchored by Custom Compiler and PrimeSim — that accelerates robust analog and mixed-signal design with best-in-class parasitic extraction, reliability analysis, and physical verification.
- Custom Compiler
- IC Validator
- NanoTime
- PrimeSim
- StarRC
- PrimeLib
- PrimeWave Design Environment
- PrimeSim Reliability
3. FPGA-based Design:
Synopsys’ FPGA synthesis solution, Synplify, accelerates time-to-shipping hardware with deep debug visibility, incremental design, broad language support, and best-in-class performance and area — including support for high-reliability and functional-safety applications.
- Synplify® FPGA synthesis software is the industry standard for producing high-performance and cost-effective FPGA designs. Synplify software supports the latest VHDL and Verilog language constructs including SystemVerilog and VHDL-2008/2019. The software also supports FPGA architectures from a variety of FPGA vendors including Achronix, Intel, Lattice, Microsemi and AMD/Xilinx, all from a single RTL and constraint source.
Verification Families: Bring-Up Software Earlier and Validate the Entire System
Verify the entire SoC with industry-leading VCS® simulation, Verdi® debug, VC SpyGlass™ RTL static signoff, VC Formal™ Apps, and silicon-proven Verification IP. Leverage the fastest emulation system on the market for earlier software bring-up, and validate the entire system with Virtualizer™ virtual prototyping and HAPS® prototyping.
Key Benefits:
- Unified Compile with VCS: Transition seamlessly between simulation, emulation, and prototyping environments
- Unified Debug with Verdi: Fix bugs across domains and abstraction levels to dramatically increase debug efficiency
- Native Integrations: Achieve higher verification productivity, performance, and throughput
Explore the Entire Synopsys Verification Family
- Debug & Verification Management
- Functional Safety
- SoC Verification Automation
- Virtual Prototyping
- VSO.ai
- Emulation
- Prototyping
- Static & Formal
- Verification Services
- FPGA Development
- Simulation
- System Test Generation
- Verification IP
